Module Name		C.1. Digital Systems / VHDL							Abbreviation		ET-DTV
Module Group			Digital Systems						mandat. [X]		option []
Summer/Winter			Summer Term				Semester Term				1
Master Program			ESD
Group			15 students
Teaching Staff			K. Mueller
Person in Charge			K. Mueller
Requirements
Course Types				Class (2 h) , Lab (2 h)
Course Objectives			The module deepens the knowledge on digital systems and enables the students to design, simulate und implement programmable logic using VHDL. The students can design complex sequential logic handle optimization and minimization of digital logic know microprocessor architectures and can develop programs in assembly and C/C++ language know the elements of VHDL can implement logic systems on FPGAs
Contents			elements of digital systems sequential systems, state machine graphs CISC- und RISC-architectures, DSPs memory and memory controllers CPLDs und FPGAs internals VHDL programming und applications communication protocols
Methods			class, labs
Literature			K. Urbanski u. R. Woitowitz: Digitaltechnik. Springer, 2000 J. Wakerly: Digital Design: Principles and Practices. Prentice-Hall, 1999 Xilinx ISE Users's Guide. Xilinx Corp., 2011
Exams			written or oral exam
Workload (h)	class		seminars/ others		labs	Home work / presentation		preparation		industry
	30		0		30	0		90		0
Language			English
Remarks
Credits			5