[modules for master programs]
© Xilinx
Table 3.1. Organization Digital Systems / VHDL
| NEWS |
On-line Classes! Please register on elli (unter ESD S20 -> ET-DTV Digital Systems/VHDL S20)
Classes and labs of this module will take place in the first half of this summer term (class 4 hours, lab 4 hours). It ends on May, 21. This module is required for SY-SOC (System-on-Chip Design) which starts on May 27 (estimated). |
| Study Program |
Master Embedded Systems Design [ESD1] |
| Course Language |
English |
| Module Description | |
| Exam (1.) | - no exam - |
| Exam (2.) | t.b.s. |
| Credits |
5 |
| Module Type |
class: 4 hours/week lab: 4 hours/week first half of summer term |
| Lecturer |
Prof. Dr. Kai Mueller |
| Start of Course |
Tuesday, April 07, 2020, 10:00h, Cisco WebEX (online) |
| End of Course |
Wednesday, May 21, 2020 (lab) |
| Class/Lab Dates |
Class #1: Monday, block 4, room S316 Class #2: Tuesday, block 3, room K02 ==> Lab participants are required to have a paper printout of the lab doc when attending the lab. Lab Group #1: Tuesday, block 4 / 5 Lab Group #2: Wednesday, block 5 / 6 Lab Group #3: Thursday, block 3 / 4 (all labs in room Z1090) |
| Documents |
[Complete Course Documentation] (updated)
[FPGA Technology Basics] (new) This material has copyright by © Xilinx University Program, © University of Strathclyde and © Steepest Ascend Ltd, 2012 [VHDL Quick Reference] © Qualis Corp. [IEEE Standard Logic Quick Reference] © Qualis Corp. |
| Mandatory Lab Reports & Deadlines |
For deadlines see lab group participants... Report #1: Moving Light (Sequential Logic Introduction) Report #2: Timed state machine (Traffic Light Controller) Report #3: Function Generator with DAC All designs must be synthesizable. Therefore the Synthesis Script must be part of the report (see below). Every report must contain names and matriculation numbers - group reports up to 3 students are allowed.
|
Examination Topics and Sample Test
|
Test question are selected from the topics below: Sample Test: ==>> [ET-DTV Sample Test] Solutions: |
Digital Systems
Number Systems / Codes
Combinational Logic
Sequential Systems, State Machines
Microprocessors, RISC and CISC Architectures
Busses, Ports
CPLDs, FPGAs
VHDL
Simulation and Verification of Digital Systems
Design of Combinational and Sequential Systems
Libraries
Intellectual Properties
K. Urbanski u. R. Woitowitz: Digitaltechnik.
Springer, 2000
J. Wakerly: Digital Design: Principles and Practices.
Prentice-Hall, 1999
J. Reichardt, B. Schwarz: VHDL-Synthese.
Oldenbourg, 2001
S. Yalamanchili: VHDL Starter's Guide.
Prentice-Hall, 1998
P. J. Ashenden: The Designer's Guide to VHDL.
Elsevier/Morgan Kaufmann, 2008
V. A. Pedroni: Circuit Design and Simulation with VHDL.
MIT Press, 2010
R. Lipsett, C. Schaefer and C. Ussery: VHDL: Hardware Description and Design.
Kluwer Academic Publishers, 1990
Xilinx Vivado Users's Guide.
Xilinx Corp., 2019
Modelsim User's Guide.
Mentor Graphics, 2010