Chapter 3. Graduate Courses of Kai Mueller
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Chapter 3. Graduate Courses of Kai Mueller

[modules for master programs]

3.1. Digital Systems / VHDL [ET-DTV / ESD1]

Virtex photo © Xilinx

Table 3.1. Organization Digital Systems / VHDL

NEWS

On-line Classes!

    Please register on elli (unter ESD S21 -> ET-DTV Digital Systems/VHDL S21)

 

Classes and labs of this module will take place in the first half of this summer term (class 4 hours, lab 4 hours). It ends on May, 19 (estimated).

This module is required for SY-SOC (System-on-Chip Design) which starts on June 07.

Study Program

Master Embedded Systems Design [ESD1]

Course Language

English

Module Description

ET-DTV

Exam (1.)

October 4, 2021

Exam (2.)

t.b.s.

Credits

5

Module Type

class: 4 hours/week

lab: 4 hours/week

first half of summer term

Lecturer

Prof. Dr. Kai Mueller

Start of Course

Monday, April 12, 2021, 08:30h, Cisco WebEX (online)

End of Course

Wednesday, June 2, 2021 (lab)

Class/Lab Dates

Class #1: Monday, block 2, (10:15h)

Class #2: Tuesday, block 4, (14:15h)

Lab #1: Tuesday, block 5 (16:00h)

Lab #2: Wednesday, block 3 (12:30h

Documents

==> Course documentation on elli

Additional Docs:

[ESD Sample Design]

[FPGA Technology Basics] (new) This material has copyright by © Xilinx University Program, © University of Strathclyde and © Steepest Ascend Ltd, 2012

[VHDL Quick Reference] © Qualis Corp.

[IEEE Standard Logic Quick Reference] © Qualis Corp.

Mandatory Lab Reports & Deadlines

For deadlines see lab group participants...

Report #1: Moving Light (Sequential Logic Introduction)

Report #2: Timed state machine (Traffic Light Controller)

Report #3: Function Generator with DAC

All designs must be synthesizable. Therefore the Synthesis Script must be part of the report (see below). Every report must contain names and matriculation numbers - group reports up to 3 students are allowed.


Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "C:/Mue/xdev14/spirxtx/spirxtx.xst" -ofn "C:/Mue/xdev14/spirxtx/spirxtx.syr"
Reading design: spirxtx.prj

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "C:\Mue\xdev14\spirxtx\spitx.vhd" into library work
Parsing entity <spitx>.
Parsing architecture <Behavioral> of entity <spitx>.
Parsing VHDL file "C:\Mue\xdev14\spirxtx\spirx.vhd" into library work
Parsing entity <spirx>.
Parsing architecture <Behavioral> of entity <spirx>.
Parsing VHDL file "C:\Mue\xdev14\spirxtx\spirxtx.vhd" into library work
Parsing entity <spirxtx>.
Parsing architecture <Behavioral> of entity <spirxtx>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

etc...

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 2.728ns (Maximum Frequency: 366.623MHz)
   Minimum input arrival time before clock: 3.567ns
   Maximum output required time after clock: 3.634ns
   Maximum combinational path delay: No path found

=========================================================================

Process "Synthesize - XST" completed successfully
    

Examination Topics and Sample Test Hot Offer

Test question are selected from the topics below:

[Topics ET-DTV]

Sample Test:

==>> [ET-DTV Sample Test]

Solutions:

==>> [Sample Test Solutions]


3.1.1. Course contents

  • Digital Systems

    • Number Systems / Codes

    • Combinational Logic

    • Sequential Systems, State Machines

    • Microprocessors, RISC and CISC Architectures

    • Busses, Ports

    • CPLDs, FPGAs

  • VHDL

    • Simulation and Verification of Digital Systems

    • Design of Combinational and Sequential Systems

    • Libraries

    • Intellectual Properties

3.1.2. Complimentary Documentation

K. Urbanski u. R. Woitowitz: Digitaltechnik. 
Springer, 2000

J. Wakerly: Digital Design: Principles and Practices. 
Prentice-Hall, 1999

J. Reichardt, B. Schwarz: VHDL-Synthese.
Oldenbourg, 2001

S. Yalamanchili: VHDL Starter's Guide.
Prentice-Hall, 1998

P. J. Ashenden: The Designer's Guide to VHDL.
Elsevier/Morgan Kaufmann, 2008

V. A. Pedroni: Circuit Design and Simulation with VHDL.
MIT Press, 2010

R. Lipsett, C. Schaefer and C. Ussery: VHDL: Hardware Description and Design.
Kluwer Academic Publishers, 1990

Xilinx Vivado Users's Guide. 
Xilinx Corp., 2019

Modelsim User's Guide.
Mentor Graphics, 2010

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2.2. Wahlveranstaltungen im Sommersemester 2021 von Kai Müller (optional courses) Home 3.2. System-on-Chip Design [SY-SOC / ESD1]